Further updates to DDR5 memory technology released from JEDEC JC-45
In August 2022 JEDEC published the new DDR5 SDRAM standard including features, functionalities, characteristics, and packages. While based on DDR4 standards, this further signaled the nearing industry transition to DDR5 server dual-inline memory modules (DIMM). DDR5 memory brings a number of key enhancements that will bring great performance and power benefits in next generation servers.
Scaling Data Rates 6.4 Gbps
While DDR4 DIMMs top out at 3.2 gigabits per second (Gbps) at a clock rate of 1.6 gigahertz (GHz), initial DDR5 will deliver a 50% bandwidth increase to 4.8 Gbps. DDR5 memory will ultimately double the data rate of DDR4 DRAM reaching 6.4 Gbps. New features, such as Decision Feedback Equalization (DFE), were also incorporated to enable the higher IO speeds.
Lower Voltage Means Lower Power
A second major change is a reduction in operating voltage (VDD) which will translate to lower power. With DDR5, the DRAM, buffer chip registering clock driver (RCD), and data buffer (DB) voltage drops from 1.2 V down to 1.1 V. However, lower VDD means smaller margin for noise immunity which designers will have to be cognizant of for their implementations.
New Power Architecture
Channel Architecture Update
Another major change is a new DIMM channel architecture. DDR4 DIMMs have a 72-bit bus, comprised of 64 data bits plus eight ECC bits. With DDR5, each DIMM will have two channels that are 40-bits wide: 32 data bits with eight ECC bits. While the data width is the same (64-bits total) having two smaller independent channels improves memory access efficiency.
In addition, DDR5 incorporates a fine grain bank refresh feature which allows some banks to refresh while others are in use, which will help lower latency. This not only causes a speed bump with DDR5, but the benefit of that higher data rate is amplified by greater efficiency. With the updated DDR5 DIMM architecture, the left and right side of the DIMM (each served by an independent 40-bit wide channel) share the RCD. To compare the two, in DDR4, the RCD provides two output clocks per side compared to the DDR5 where the RCD provides four output clocks per side. This means the highest density DIMMs with x4 DRAMs, will allow each group of 5 DRAMs (single rank, half-channel) to receive its own independent clock. Giving each rank and half-channel an independent clock improves signal integrity, helping to address the lower noise margin issue raised by lowering the VDD.
A fifth and final change to highlight is DDR5’s support for higher capacity DRAM devices. With DDR5 buffer chip DIMMs, the server or system designer can use densities of up to 64 Gb DRAMs in a single-die package. DDR4 maxes out at 16 Gb DRAM in a single-die package (SDP). DDR5 supports features like on-die ECC, error transparency mode, post-package repair, and read and write CRC modes to support higher-capacity DRAMs. The impact of higher capacity devices obviously translates to higher capacity DIMMs. So, while DDR4 DIMMs can have capacities of up to 64 GB (using SDP), DDR5 SDP based DIMMs quadruple that to 256 GB.
AMP, Inc. Memory Modules
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